In high speed digital circuitry and especially divider circuits it is often desirable to normalize data stored in registers prior to performing various mathematical operations, such as dividing. Normalization is the shifting of data in a register, such as a shift register, toward the most significant bit stage until the first significant bit in the data has been shifted into the most significant bit stage. In some instances the most significant bit stage in a register may be utilized to store a sign bit and the data is considered normalized when the first significant bit in the data is shifted into the second most significant bit stage.
In the prior art, data stored in shift registers is normalized in one of two ways. In a first method of normalization relatively complicated sensing circuitry is utilized to determined the position of the first significant bit of the data relative to the most significant bit stage of the shift register. A signal is then supplied to shifting circuitry which shifts the data as many stages as required in a single clock pulse. Circuitry of this type is disclosed in copending U.S. application entitled "Digital Scaling Apparatus", Ser. No. 06/134,859, filed Mar. 28, 1980 now U.S. Pat. No. 4,335,372, issued June 15, 1982.
In a second type of normalizing circuitry the data is stored in a shift register and shifted serially, one stage per clock pulse, until the first significant bit of data is shifted into the most significant bit stage. This prior art method of normalization requires a larger number of clock pulses, since the date could be shifted the entire length of the shift register.
In digital non-restoring divider circuits, wherein the dividend or remainder is compared to the divisor, multiplied by two or shifted one stage, and the divisor is added or substracted with the shifted dividend in each of a plurality of operations, it is not uncommon for prior art circuitry to require four or five clock pulses to execute each of the plurality of one bit by n bit operations or divisions.